The fabrication of integrated circuits often involves one or more steps of electroplating a layer of conductive metal onto the surface of a semiconductor wafer. For example, in some IC fabrication procedures, an electroplating operation may be used to fill with metal the various features formed in the surface of a semiconductor wafer such as, for instance, the trenches and vias used as conductive paths between various circuit elements. The electroplated metal is oftentimes copper, but depending on the IC design, other metals may be appropriate and/or advantageous including ruthenium, palladium, iridium, rhodium, osmium, cobalt, nickel, gold, silver, and aluminum. In some embodiments, alloys of these metals may be appropriate and/or advantageous.
In a typical electroplating operation, the surface of the wafer is exposed to an electroplating bath fluid which contains dissolved ions of the metal to be electroplated, and an electrical circuit is created between an electrode in the bath (which serves as an anode) and surface of the wafer (which serves as the cathode). Flow of current through this circuit upon application of an applied voltage causes electrons to flow to the cathode surface and reduce dissolved metal ions in its vicinity thereby resulting in the plating out of solution of neutral elemental metal onto the surface of the wafer.
However, for this circuit to be completed and for electrochemical reduction of dissolved metal ions to occur, the surface of the wafer (serving as the circuit's cathode) must be, at least to a certain extent, relatively conductive. Accordingly, since the bare surface of a semiconductor wafer is not generally substantially conductive, the actual electroplating step in an electroplating operation is often preceded by the deposition of a conductive seed layer which provides the necessary conductive surface. Deposition of the seed layer may be accomplished by any feasible method of depositing the seed material. Suitable methods may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), conformal film deposition (CFD), atomic layer deposition (ALD), and the like. Oftentimes, seed layer deposition and electroplating is followed by an edge bevel removal (EBR) operation that removes seed metal deposited at the edge of the wafer where its presence is not desired via the application of a thin viscous flow of etchant solution over the wafer's edge.
However, oftentimes, after the seed layer is deposited, a wafer is removed from vacuum and exposed to clean room ambient air. In some instances, there could be a queue time ranging from a few minutes to several hours before the wafer is electroplated. Delay time and associated exposure to ambient air can cause oxidation of the seed layer—often referred to as “seed aging.” This oxide layer resulting from seed aging, being substantially non-conductive, may act to reduce electroplating efficiency or even prevent it from occurring. In addition, the surface wetting characteristics of the wafer may change also contributing to defects on the wafer. Post-electroplating voids and pits have been seen on pattern wafers as a result of too much pre-electroplating seed aging resulting in useless IC devices and thus negatively impacting overall wafer yields. Moreover, it is observed that seed aging effects are exacerbated in lower technology nodes—sub 22 nm, for example—where seed layers are generally very thin, for example, in some circumstances 50 Å or less. Seed dissolution and reduction in current density is also seen with thinner seed in localized spots deeper into the vias and trenches with higher denser pattern densities, also causing post-electroplating wafer defects. Accordingly, methods and apparatuses have been developed to deal with oxide layer reduction and/or removal, and further improvements on these methods and apparatuses are disclosed herein.